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40611hkim 20110328-s00003 no.a1228-1/25 ver.0.7 lc88f83b0a overview the lc88f83b0a is a 16-bit microcontroller, centered around an xstormy16 cpu, integrates on a single chip a number of hardware features such as 32-bit program counter, 16 bits 16 general purpose register, 128k-byte flash rom (onboard programmable), 4096-byte ram, lcd display dedicated ram, lcd dot matrix driver, on-chip debugging function, programmable timer, a base timer serving as a tim e-of-day clock, a synchronous sio interface with automatic transmission capability, an asyn chronous sio (uart) interface, a 12-/8-bit resolution 4-channel ad converter, and a 12-source 11-vector interrupt feature. features ? flash rom ? 128k 8bit (table data reside in the same space.) ? ram ? 4240 8bit ? for data 4096 8bit ? for display 72 16bit ? lcd display ? 64 segment 16 common/72 segment 8 common (1/4 bias) ordering number : ena1228 cmos ic from 128k byte, ram 4096k byte on-chip 16-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
lc88f83b0a no.a1228-2/25 ? instruction execution time (min) ? 31.0 s : 32.768khz crystal used ? 15.6 s (typ) : low speed rc oscillation (typ: 64khz) ? 0.25 s : 4.0mhz ceramic filter oscillation ? 1.00 s (typ) : high speed rc oscillation (typ: 1mhz) ? power supply voltage ? 2.3v to 5.5v (ta =-20 to 75 c) : 32.768khz crystal used ? 2.3v to 5.5v (ta =0 to 60 c) : low speed rc oscillation (typ: 64khz) ? 2.4v to 5.5v (ta =-20 to 75 c) : 4.0mhz ceramic filter oscillation ? 2.3v to 5.5v (ta =0 to 60 c) : high-speed rc oscillation (typ: 1mhz) ? 2.4v to 5.5v (ta =-20 to 75 c) : when lcd on ? consumption current (3.0v): ? 10.5 a (typ) (ta=25 c, crystal oscillation 32.768khz, 1/1 dividing frequency, halt, lcd: on) ? 300 a (typ) (ta=25 c, crystal oscillation 32.768khz, cf 4mhz, 1/2 dividing frequency, halt, lcd: on) ? 2200 a (typ) (ta=25 c, crystal oscillation 32.768khz, cf 4mhz, 1/2 divi ding frequency, continuous operation, lcd: on) ? ports ? normal withstand voltage i/o ports 20 (p0n, p1n, p20 to p23) ? lcd (com8/seg0 to com15/seg7 pins are multiplexed with common and segment) lcd drive bias power supply port 4 (v lcd 1 to v lcd 4) step-up capacitor port 2 (cup00, cup01) 16 common mode segment output 64 (seg8 to seg71) common output 16 (com0 to com15) 8 common mode segment output 72 (seg0 to seg71) common output 8 (com0 to com7) ? oscillation pins 4 (xt1, xt2, cf1, cf2) ? reset pin 1 (resb) ? test pin 1 (tst) ? lcd port power pins 2 (lcdv ss 0, lcdv ss 1) ? power pins 2 (v dd , v ss ) ? lcd ? lcd power supply : capacitor step-up type ? number of dots : 1024 (64 segments 16 commons) / 576 (72 segments 8 commons) ? contrast : adjustable in 16 steps ? lcd frame frequency : selectable from 4 types
lc88f83b0a no.a1228-3/25 ? timers ? timer 0: 16-bit timer that supports pwm/toggle outputs 1) with 5-bit prescaler 2) 8-bit pwm 2/8-bit timer + 8-bit pwm mode selectable 3) clock source selectable from system clock, osc0, osc1, and internal rc oscillator ? timer 1: 16-bit timer with capture registers 1) with 5-bit prescaler 2) may be divided into 2 channels of 8-bit timer 3) clock source selectable from system clock, osc0, osc1, and internal rc oscillator ? timer 3: 16-bit timer that supports pwm/toggle outputs 1) with 8-bit prescaler 2) 8-bit timer 2ch/8-bit timer + 8-bit pwm mode selectable 3) clock source selectable from system clock, osc0, osc1, and internal rc oscillator ? timer 4: 16-bit timer that supports toggle outputs 1) clock source selectable from system clock and prescaler 0 ? timer 5: 16-bit timer that supports toggle outputs 1) clock source selectable from system clock and prescaler 0 ? base timer 1) clock may be selected from osc0 (32.768khz crystal os cillator) and frequency-divided output of system clock. 2) interrupts can be generated in 7 timing schemes. ? watchdog timer 1) driven by the base timer + internal watchdog timer dedicated counter. 2) interrupt or reset mode selectable ? sio0: 8-bit synchronous sio 1) lsb first/msb first mode selectable 2) it is possible to communicate with 8 bits or less. (1 to 8 bits specifiable in 1-bit units) 3) built-in 8-bit baudrate generator (transfer clock cycle 4 tcyc to 512 tcyc) 4) automatic continuous data transmission (9 to 32768 bits specifiable in 1-bit units) 5) interval function (interval time: 0 to 64 sioclks specifiable in 1 sioclk units) 6) wakeup function ? uart2: asynchronous sio 1) full duplex transmission 2) start bit 1, data bit 8 (lsb first), stop bit 1 3) parity bit: none/even parity/odd parity 4) transfer rate: 8 to 4096 tcyc 5) baudrate source clock: systemclock/osc0/osc1 6) wakeup function ? ad converter: 12bit 4 channels 1) 12-/8-bit resolution selectable 2) analog input: 4 channels 3) comparator mode 4) automatic reference voltage generation
lc88f83b0a no.a1228-4/25 ? interrupts ? 12 sources, 11 vector addresses 1) provides three levels of multiplex interrupt control. any in terrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address interrupt source 1 08000h watchdogtimer 2 08004h basetimer 3 08008h timer0 4 08018h sio0 5 0801ch timer1 6 08020h uart2 7 08024h timer3 8 08028h timer4 9 0802ch timer5 10 08030h adc 11 0803ch p00 to p05 seg71 to seg64 ? the priority level can be specified by three levels. ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels ? max- whole ram area (stack is set in ram) ? oscillation circuits ? osc1: for system clock ceramic oscillation with external cgc, cdc or rc oscillation (external rcr1) ? osc0: for low-speed system clock, base timer count, for lcd display 32khz crystal oscillation with external cgx, cdx or rc oscillation (external rcr0) ? internal oscillation circuit: internal rc * depends on control resister for each oscillator operation and stop. initial setting - external oscillation stop, internal rc oscillation operation
lc88f83b0a no.a1228-5/25 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) released by a system reset or occurrence of an interrupt. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) osc1, internal rc and x?tal oscillators automatically stop operation. 2) there are the following methods of resetting the hold. (1) setting the reset pin to the low level (2) having an interrupt source established in the sio0 (3) having an interrupt source established in the uart2 (4) having an interrupt source established in the p00 to p05 (5) having an interrupt source established in the seg71 to seg64 ? x?tal hold mode: suspends instruction execution and the op eration of the peripheral ci rcuits except using osc0. 1) the osc1 and internal rc oscillators automatically stop operation. 2) the state of osc0 oscillation established wh en the x'tal hold mode is entered is retained. 3) there are the following methods of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) having an interrupt source established in the base timer circuit (3) having an interrupt source established in the timers 0, 1, 3, 4, 5 (4) having an interrupt source established in the sio0 (5) having an interrupt source established in the uart2 (6) having an interrupt source established in the p00 to p05 (7) having an interrupt source established in the seg71 to seg64 ? on-chip debugger ? supports software debugging with the ic mounted on the target board. ? supports tracing, realtime monitoring, and breakpoint setting. ? single-wire communication ? package form ? tqfp120(14 14): lead-free type ? development tools ? on-chip debugger : eocuif1 + lc88f83b0a ? programming boards : package dimensions unit : mm (typ) 3257a sanyo : tqfp120(14x14) 0.125 120 0.15 0.4 (1.2) 1 14.0 16.0 14.0 16.0 1.2max 0.1 (1.0) 0.5
lc88f83b0a no.a1228-6/25 pad assignment ? chip size (x y) : 3.40mm 3.19mm ? pad size : 59 m ? pad pitch : 80 m ? chip thickness : 280 m 20 m note: pin numbers assigned to a package differ from pad numbers assigned to a chip. numbers in the above figure show the pad numbers of the chip. 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 y x (0, 0)
lc88f83b0a no.a1228-7/25 pad coordinates table coordinates coordinates pad no. pin name x m y m pad no. pin name x m y m 1 p20 1567.4 -1308 48 seg29 -192 1462.4 2 p21 1567.4 -1228 49 seg28 -272 1462.4 3 p22 1567.4 -1147 50 seg27 -352 1462.4 4 p23 1567.4 -1067 51 seg26 -432 1462.4 5 seg71 1606.99 -951.8 52 seg25 -512 1462.4 6 seg70 1606.99 -863.6 53 seg24 -592 1462.4 7 seg69 1606.99 -775.4 54 seg23 -672 1462.4 8 seg68 1606.99 -606.8 55 seg22 -752 1462.4 9 seg67 1606.99 -518.6 56 seg21 -832 1462.4 10 seg66 1606.99 -430.4 57 seg20 -912 1462.4 11 seg65 1606.99 -342.2 58 seg19 -992 1462.4 12 seg64 1606.99 -254 59 seg18 -1072 1462.4 13 seg63 1606.99 -165.8 60 seg17 -1152 1462.4 14 seg62 1606.99 -77.6 61 seg16 -1232 1462.4 15 seg61 1606.99 10.6 62 seg15 -1567.4 1335 16 seg60 1606.99 98.8 63 seg14 -1567.4 1255 17 seg59 1606.99 187 64 seg13 -1567.4 1175 18 seg58 1606.99 275.2 65 seg12 -1567.4 1095 19 seg57 1606.99 363.4 66 seg11 -1567.4 1015 20 seg56 1606.99 451.6 67 seg10 -1567.4 935 21 seg55 1567.4 573 68 seg9 -1567.4 855 22 seg54 1567.4 653 69 seg8 -1567.4 775 23 seg53 1567.4 733 70 - - - 24 seg52 1567.4 813 71 com15/seg7 -1567.4 615 25 seg51 1567.4 893 72 - - - 26 seg50 1567.4 973 73 com14/seg6 -1567.4 455 27 seg49 1567.4 1053 74 - - - 28 seg48 1567.4 1133 75 com13/seg5 -1567.4 295 29 seg47 1567.4 1213 76 - - - 30 seg46 1567.4 1293 77 com12/seg4 -1567.4 135 31 lcdv ss 1 1190 1462.4 78 - - - 32 seg45 1088 1462.4 79 com11/seg3 -1567.4 -25 33 seg44 1008 1462.4 80 - - - 34 seg43 928 1462.4 81 com10/seg2 -1567.4 -185 35 seg42 848 1462.4 82 - - - 36 seg41 768 1462.4 83 com9/seg1 -1567.4 -345 37 seg40 688 1462.4 84 - - - 38 seg39 608 1462.4 85 com8/seg0 -1567.4 -505 39 seg38 528 1462.4 86 com7 -1567.4 -585 40 seg37 448 1462.4 87 com6 -1567.4 -665 41 seg36 368 1462.4 88 com5 -1567.4 -745 42 seg35 288 1462.4 89 com4 -1567.4 -825 43 seg34 208 1462.4 90 com3 -1567.4 -905 44 seg33 128 1462.4 91 com2 -1567.4 -985 45 seg32 48 1462.4 92 com1 -1567.4 -1065 46 seg31 -32 1462.4 93 com0 -1567.4 -1145 47 seg30 -112 1462.4 94 lcdv ss 0 -1567.4 -1240 continued on next page.
lc88f83b0a no.a1228-8/25 continued from preceding page. coordinates coordinates pad no. pin name x m y m pad no. pin name x m y m 95 cup00 -1567.4 -1335.8 111 p00 205 -1462.4 96 cup01 -1567.4 -1415.8 112 p01 285 -1462.4 97 v lcd 4 -1295.45 -1462.4 113 p02 365 -1462.4 98 v lcd 3 -1215.45 -1462.4 114 p03 445 -1462.4 99 v lcd 2 -1130.8 -1462.4 115 p04 525 -1462.4 100 v lcd 1 -1050.8 -1462.4 116 p05 605 -1462.4 101 tst -965 -1462.4 117 p06 685 -1462.4 102 xt2 -723 -1462.4 118 p07 765 -1462.4 103 xt1 -643 -1462.4 119 p10 845 -1462.4 104 resb -563 -1462.4 120 p11 925 -1462.4 105 -383.5 -1462.4 121 p12 1005 -1462.4 106 v dd -272.5 -1462.4 122 p13 1085 -1462.4 107 cf1 -172 -1462.4 123 p14 1165 -1462.4 108 cf2 -92 -1462.4 124 p15 1245 -1462.4 109 3 -1462.4 125 p16 1325 -1462.4 110 v ss 108 -1462.4 126 p17 1405 -1462.4 note: ? pad coordinates shown in above table are referenced at the center of the ic-chip as an origin. ? there are two pads for each v dd and v ss , and each set of pads needs double-bonding. pin assignment sanyo: tqfp120(14 14) ?lead-free type? lc88f83b0a 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 v lcd 4 v lcd 3 v lcd 2 v lcd 1 tst xt2 xt1 resb v dd cf1 cf2 v ss p00/p0li p01/p0li p02/p0li p03/p0li p04/p0hli p05/p0hli p06/t0pwml p07/t0pwmh p10/si0o p11/si0io p12/si0clk p13/t3ol p14/t3oh p15 p16/u2rx p17/u2tx seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 lcdv ss 1 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg8 seg9 com15/seg7 com14/seg6 com13/seg5 com12/seg4 com11/seg3 com10/seg2 com9/seg1 com8/seg0 com7 com6 com5 com4 com3 com2 com1 com0 lcdv ss 0 cup00 cup01 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56/sno15/sgin15 seg57/sno14/sgin14 seg58/sno13/sgin13 seg59/sno12/sgin12 seg60/sno11/sgin11 seg61/sno10/sgin10 seg62/sno9/sgin9 seg63/sno8/sgin8 seg64/sno7/sgin7/sgint7 seg65/sno6/sgin6/sgint6 seg66/sno5/sgin5/sgint5 seg67/sno4/sgin4/sgint4 seg68/sno3/sgin3/sgint3 seg69/sno2/sgin2/sgint2 seg70/sno1/sgin1/sgint1/t3ih seg71/sno0/sgin0/sgint0/t3il p23/an3 p22/an2 p21/an1/t5o p20/an0/t4o 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 top view
lc88f83b0a no.a1228-9/25 pin no. name pin no. name pin no. name pin no. name 1 v lcd 4 31 p20/an0/t4o 61 lcdv ss 1 91 2 v lcd 3 32 p21/an1/t5o 62 seg45 92 seg16 3 v lcd 2 33 p22/an2 63 seg44 93 seg15 4 v lcd 1 34 p23/an3 64 seg43 94 seg14 5 tst 35 seg71/sno0 /sgin0/sgint0 /t3il 65 seg42 95 seg13 6 36 seg70/sno1 /sgin1/sgint1 /t3ih 66 seg41 96 seg12 7 xt2 37 seg69/sno2 /sgin2/sgint2 67 seg40 97 seg11 8 xt1 38 seg68/sno3 /sgin3/sgint3 68 seg39 98 seg10 9 resb 39 seg67/sno4 /sgin4/sgint4 69 seg38 99 seg9 10 v dd 40 seg66/sno5 /sgin5/sgint5 70 seg37 100 seg8 11 cf1 41 seg65/sno6 /sgin6/sgint6 71 seg36 101 com15/seg7 12 cf2 42 seg64/sno7 /sgin7/sgint7 72 seg35 102 com14/seg6 13 v ss 43 seg63/sno8 /sgin8 73 seg34 103 com13/seg5 14 p00/p0li 44 seg62/sno9 /sgin9 74 seg33 104 com12/seg4 15 p01/p0li 45 seg61/sno10 /sgin10 75 seg32 105 com11/seg3 16 p02/p0li 46 seg60/sno11 /sgin11 76 seg31 106 com10/seg2 17 p03/p0li 47 seg59/sno12 /sgin12 77 seg30 107 com9/seg1 18 p04/p0hli 48 seg58/sno13 /sgin13 78 seg29 108 com8/seg0 19 p05/p0hli 49 seg57/sno14 /sgin14 79 seg28 109 com7 20 p06/t0pwml 50 seg56/sno15 /sgin15 80 seg27 110 com6 21 p07/t0pwmh 51 seg55 81 seg26 111 com5 22 p10/si0o 52 seg54 82 seg25 112 com4 23 p11/si0io 53 seg53 83 seg24 113 com3 24 p12/si0clk 54 seg52 84 seg23 114 com2 25 p13/t3ol 55 seg51 85 seg22 115 com1 26 p14/t3oh 56 seg50 86 seg21 116 com0 27 p15 57 seg49 87 seg20 117 lcdv ss 0 28 p16/u2rx 58 seg48 88 seg19 118 cup00 29 p17/u2tx 59 seg47 89 seg18 119 cup01 30 60 seg46 90 seg17 120
lc88f83b0a no.a1228-10/25 system block diagram p00 to 07 p10 to 17 com 0 to 15 resb tst xt1 xt2 cf1 cf2 cup00, 01 v lcd 1 to 4 lcd segment driver 72 terminals common driver 16 terminals (adc 4 terminals) (i/o 16 terminals) on-chip debugger seg 71 to 56 timer 1 i/o port timer 0 r0 to r15 alu ram (4k 8bit) base timer interrupt control rom (128k8bit) pc wd timer ir system control standby control internal rc osc1 cf rc osc0 x?tal rc clock timer 3 psw lcd display ram 72 16bit uart2 sio0 i/o port lcd power supply timer 4 timer 5 p20 to 23 i/o port seg 0 to 71
lc88f83b0a no.a1228-11/25 pin description pin name i/o description v dd - + power supply pin v ss - - power supply pin v lcd 1 to 4 - lcd bias power port (capacitor connection port) lcdv ss 0, lcdv ss 1 - lcd power supply pin cup00, 01 - switching pin for generating lcd driving voltage connect capacitor between both ports. xt1 i osc0 xt2 o oscillator circuit for system clock (low speed) ? 32.768khz crystal oscillator and c apacitor for oscillation connection ? xt1: resistor connection for rc oscillation (rc model) cf1 i osc1 cf2 o oscillator circuit for system clock (high speed) ? ceramic oscillator and capacitor for oscillator connection ? cf1: resistance connection for rc oscillator (rc model) port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? shared pins p00 to p05 : interrupt function p06: timer 0 pwml output p07: timer 0 pwmh output port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? shared pins p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: timer 3 pwml output p14: timer 3 pwmh output p16: uart 2 receive p17: uart 2 send port 2 p20 to p23 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units p20 to p23: ad converter input ports (an0 to an3) ? shared pins p20: timer 4 output p21: timer 5 output com0 to com7 o ? lcd common output port com8/seg0 to com15/seg7 o ? lcd common output port/segment output port common output/segment output is sw itched according to the register. seg8 to seg55 o ? lcd segment output port seg56 to seg71 i/o ? lcd segment output port ? seg71 to seg56: general purpose nch od output/general purpose input seg71 to seg56 can switch lcd output, a general-pur pose nch od output, and a general-purpose input (every 4 bits). ? seg71 to seg64: interrupt function (every 4 bits) selecting sampling frequency for chattering removal (every 4 bits) level/edge selection (every 4 bits) hi/low level or rise/fall selection (every 1 bit) ? seg71 to seg70: timer 3 external input resb i ? input terminal for system initialization it operates reset by the ?low? input. with pull-up resistor tst i/o ? test pin ? on-chip debugger communication terminal used with pull-down or v ss *connect 100k between this pin and v ss when on-chip debugger is used.
lc88f83b0a no.a1228-12/25 application circuit x'tal crystal oscillator c gx trimmer capacitor c dx capacitance for x?tal r cr0 resistor for low-speed oscillation *4: rc oscillation specification c cr0 capacitor for low-speed oscillation *4: rc oscillation specification (**1) (**1) 0.1 f capacitor is recommended when using xt1/xt2 as a system clock. cf ceramic oscillator c gc capacitance for cf c dc capacitance for cf r cr1 resistor for high-speed oscillation *5: rc oscillation specification c cr1 capacitor for high-speed oscillation *5: rc oscillation specification c1 to c5 capacitor c den electrolytic capacitor c res capacitance for resb r tst resister when on-chip debugger is used lcd panel 64 16/72 8 lc88f83b0a cup01 cup00 v lcd 4 v lcd 3 v lcd 2 v lcd 1 c1 c2 c3 i/o c4 c5 v dd v ss lcdv ss 0 lcdv ss 1 tst *1: crystal oscillation *2: internal rc oscillation *3: ceramic oscillation 2.3v to 5.5v c den c res + *1 *5 *3 p00 p01 p02 p03 p04 p05 p06 p07 seg8 seg71 com8/seg0 cf2 xt2 xt1 r cr1 r cr0 x'tal c gx c dx c gc c dc resb c cr1 i/o p10 (sio0-out) p11 (sio0-in) p12 (sio0-clk) p13 p14 p15 p16 (uart2-rx) p17 (uart2-tx) uart device *4 c cr0 com0 com7 com15/seg7 i/o p20 p21 p22 p23 pulse output r tst on-chip debugger cf1 cf
lc88f83b0a no.a1228-13/25 absolute maximum ratings at ta = 25c, v ss = lcdv ss 0 = lcdv ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd v dd -0.3 +6.5 lcd supply voltage v lcd max v lcd 2 to v lcd 4 v dd -0.3 +6.5 lcd maximum supply voltage lcd max seg0 to seg71 com0 to com15 v dd , v lcd 4 -0.3 +6.5 input voltage v i (1) resb, xt1, cf1 -0.3 v dd +0.3 input/output voltage v io (1) port 0, 1, 2 seg71 to seg56 -0.3 v dd +0.3 v ioph(1) port0, 2 cmos output selected current at each pin -5 peak output current ioph(2) port1 cmos output selected current at each pin -14 iomh(1) port0, 2 cmos output selected current at each pin -3 mean output current (note 1-1) iomh(2) port1 cmos output selected current at each pin -9 ioah(1) port0, 2 total of all pins 22.5 ioah(2) port1 total of all pins 25 high level output current total output current ioah(3) port 0, 1, 2 total of all pins 47.5 iopl(1) port0, 2 current at each pin 13 peak output current iopl(2) port1 current at each pin 17 ioml(1) port0, 2 current at each pin 7.5 mean output current (note 1-1) ioml(2) port1 current at each pin 10.5 ioal(1) port0, 2 total of all pins 35 ioal(2) port1 total of all pins 60 low level output current total output current ioal(3) port 0, 1, 2 total of all pins 80 ma allowable power dissipation pd max tqfp120(1414) ta=-20 to +75 c 250 mw operating ambient temperature topg -20 75 storage ambient temperature tstg -65 125 c note 1-1: the mean output current is a mean value measured over 100ms. note: we assume that the measurements for the allowable operating ranges and el ectrical characteristics described in this document are performed with the chip mounted in a package. although this product is shipped in chip form, the charact eristic values listed in this document are measured with this ic mounted on a sanyo-designated package at operating ambient temperature range of -20c to +70c. the specifications of this product in package form or in chip forms ar e basically identical, however, the characteristics of the product in chip form may vary depending on the board on which the product is mounted, the bonding pressure, and the type of mold resin used.
lc88f83b0a no.a1228-14/25 allowable operating conditions at ta = -20c to +75c, v ss = lcdv ss 0 = lcdv ss 1 = 0v ratings parameter symbol pin /remarks conditions v dd [v] min typ max unit 0.238 s tcyc 100 s 2.6 5.5 0.476 s tcyc 100 s 2.4 5.5 operating supply voltage (note2-1) v dd (1) v dd 0.909 s tcyc 100 s 2.3 5.5 lcd drive voltage v lcd (1) v lcd 2 to v lcd 4 5.5 memory sustaining supply voltage vhd v dd ram and register contents sustained in hold mode. 2.0 5.5 v ih (1) port 0, 1 output disabled 0.30v dd +0.70 v dd high level input voltage v ih (2) resb 0.75v dd v dd v il (1) port 0, 1 output disabled v ss 0.10v dd +0.40 low level input voltage v il (2) resb v ss 0.25v dd v crystal oscillation 2.3 to 5.5 32.768 fosc0 xt1, xt2 low speed rc oscillation (note2-2) 2.3 to 5.5 30 80 ceramic oscillation 2.4 to 5.5 400 4200 2.4 to 5.5 400 4200 fosc1 cf1, cf2 high-speed rc oscillation (note2-2) 2.3 to 5.5 400 1100 oscillating frequency range (note2-3) fintrc internal rc oscillation 1000 khz note2-1: v dd must be held greater than or equal to 2.7v in the flash rom onboard programming mode. note2-2: ta=0 c to 60 c note2-3: the parts value of oscillation circ uit is shown in table 1 and table 2.
lc88f83b0a no.a1228-15/25 electrical characteristics at ta = -20c to +75c, v ss = lcdv ss 0 = lcdv ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) port 0, 1, 2 output disabled pull-up resister off v in =v dd (including off state leak current of the output tr.) 2.7 to 5.5 1 high level input current i ih (2) resb v in =v dd 2.7 to 5.5 1 i il (1) port 0, 1, 2 output disabled pull-up resister off v in =v ss (including off state leak current of the output tr.) 2.7 to 5.5 -1 i il (2) 4.5 to 5.5 -117 -25 i il (3) port 0, 1, 2 2.7 to 3.0 -31 -5.8 i il (4) 4.5 to 5.5 -10.2 -3.7 low level input current i il (5) resb output disabled pull-up resister on v in =v ss (including off state leak current of the output tr.) 2.7 to 3.0 -6.3 -2.4 a i oh (1) 4.5 to 5.5 -3.7 i oh (2) cmos output mode port0, 2 2.7 to 3.0 -1.6 i oh (3) 4.5 to 5.5 -10 high level output current i oh (4) cmos output mode port1 v oh (1)=v dd -1.0v 2.7 to 3.0 -4.5 i ol (1) 4.5 to 5.5 10 i ol (2) port0, 2 2.7 to 3.0 4.4 i ol (3) 4.5 to 5.5 14.5 i ol (4) port1 2.7 to 3.0 6.5 i ol (5) 4.5 to 5.5 0.5 low level output current i ol (6) seg71 to seg56 v ol (1)=v ss +1.0v 2.7 to 3.0 0.5 ma i oh (5) v oh (2)=v lcd 4-0.05v -25 common output current i ol (7) com0 to com15 v ol (2)=v ss +0.05v 2.7 to 5.5 25 a i oh (6) v oh (2)=v lcd 4-0.05v 2.7 to 5.5 -10 segment output current i ol (8) seg0 to seg71 v ol (2)=v ss +0.05v 10 hysterisis voltage vhys(1) port 0, 1, 2 resb 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.7 to 5.5 10 pf
lc88f83b0a no.a1228-16/25 lcd drive voltage at ta = -20c to +75c, v ss = lcdv ss 0 = lcdv ss 1 = 0v special notes: 0.1 f capacitor must be connected to v lcd 1, v lcd 2, v lcd 3, and v lcd 4. (with no panel load) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit contrast ?00? 1.030 contrast ?01? 1.045 contrast ?02? 1.060 contrast ?03? 1.075 contrast ?04? 1.090 contrast ?05? 1.105 contrast ?06? 1.120 contrast ?07? 1.135 contrast ?08? 1.150 contrast ?09? 1.165 contrast ?10? 1.180 contrast ?11? 1.195 contrast ?12? 1.210 contrast ?13? 1.225 contrast ?14? 1.240 v lcd 1 v dd v lcd 1 contrast ?15? typ 0.88 1.255 typ 1.10 v lcd 2 2v lcd 1 v lcd 3 3v lcd 1 lcd drive voltage v lcd 4 2.4 to 5.5 4v lcd 1 v
lc88f83b0a no.a1228-17/25 serial i/o characteristics at ta = -20c to +75c, v ss = lcdv ss 0 = lcdv ss 1 = 0v 1. sio0 serial i/o characteristics (wake-up function is not in use) (note 4-1-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(1) 4 low level pulse width tsckl(1) 2 tsckh(1) see fig. 6. 2 tsckha(1) automatic communication mode see fig. 6. 6 tsckhbsy(1a) automatic communication mode see fig. 6. 23 input clock high level pulse width tsckhbsy(1b) sck0(p12) excluding automatic communication mode see fig. 6. 2.3 to 5.5 4 frequency tsck(2) 4 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) cmos output selected see fig. 6. 1/2 tsck tsckha(2) automatic communication mode cmos output selected see fig. 6. 6 tsckhbsy(2a) automatic communication mode cmos output selected see fig. 6. 4 23 serial clock output clock high level pulse width tsckhbsy(2b) sck0(p12) excluding automatic communication mode see fig. 6. 2.3 to 5.5 4 tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) si0(p11), sb0(p11) must be specified with respect to rising edge of sioclk. see fig. 6. 2.3 to 5.5 0.03 input clock tdd0(1) (note4-1-2) 1tcyc +0.05 serial output output clock output delay time tddo(2) so0(p10), sb0(p11) (note4-1-2) 2.3 to 5.5 1tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig.6.
lc88f83b0a no.a1228-18/25 2. sio1 serial i/o characteristics (wake-up function is not in use) (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 tsckh(3) 1 serial clock input clock high level pulse width tsckhbsy(3) sck0(p12) see fig. 6. 2.3 to 5.5 2 tcyc data setup time tsdi(2) 0.03 serial input data hold time thdi(2) si0(p11), sb0(p11) must be specified with respect to rising edge of sioclk. see fig. 6. 2.3 to 5.5 0.03 serial output input clock output delay time tdd0(3) so0(p10), sb0(p11) (note4-2-2) 2.3 to 5.5 1tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. note 4-2-2: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig.6. uart2 operating conditions at ta = -20 to +75 c, v ss = lcdv ss 0 = lcdv ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit transfer rate ubr2 urx2(p16), utx2(p17) 2.3 to 5.5 8 4096 tcyc pulse input conditions at ta = -20 to +75 c, v ss = lcdv ss 0 = lcdv ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit high/low level pulse width tpil(1) resb resetting is enabled. 2.3 to 5.5 50 s
lc88f83b0a no.a1228-19/25 ad converter characteristics at v ss = lcdv ss 0 = lcdv ss 1 = 0v <12-bits ad converter mode/ta= -10 c to +75 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.9 to 5.5 12 bit absolute accuracy et (note7-1) 2.9 to 5.5 16 lsb conversion time tcad see conversion time calculation formulas. (note7-2) 2.9 to 5.5 90 130 s analog input voltage range vain 2.9 to 5.5 v ss v dd v iainh vain=v dd 2.9 to 5.5 1 analog ports input current iainl an0(seg71) to an3(seg68) vain=v ss 2.9 to 5.5 -1 a <8-bits ad converter mode/ta= -10 c to +75 c > specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.9 to 5.5 8 bit absolute accuracy et (note7-1) 2.9 to 5.5 1.5 lsb conversion time tcad see conversion time calculation formulas. (note7-2) 2.9 to 5.5 55 75 s analog input voltage range vain 2.9 to 5.5 v ss v dd v iainh vain=v dd 2.9 to 5.5 1 analog ports input current iainl an0(seg71) to an3(seg68) vain=v ss 2.9 to 5.5 -1 a 12-bits ad converter mode: tcad (conversion time) = ((52/(division ratio))+2) tcyc 8-bits ad converter mode: tcad (conver sion time) = ((32/(division ratio))+2) tcyc ad conversion time (tcad)[ s] external oscillator fmcf[mhz] operating supply voltage range v dd [v] system division ratio (sysdiv) cycle time tcyc [ns] ad division ratio (addiv) 12-bit ad 8-bit ad 1/1 250 1/8 104.5 64.5 cf-4 2.9 to 4.0 1/2 500 1/4 105.0 65.0 note 7-1: the quantization error ( 1/2lsb) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 7-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12 -bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
lc88f83b0a no.a1228-20/25 consumption current characteristics at ta = -20 to +75 c, v ss = lcdv ss 0 = lcdv ss 1 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) 2.4 to 5.5 70 150 iddop(2) lcd display on 2.4 to 3.6 50 80 iddop(3) 2.3 to 5.5 70 120 iddop(4) crystal oscillation mode ? fosc0=32.768khz ? system clock: fosc0 ? internal rc oscillation stopped ? fosc1=0hz (oscillation stop) ? 1/1frequency division ratio. [no panel load] lcd display off 2.3 to 3.6 40 70 iddop(5) 2.4 to5.5 3000 4100 iddop(6) ceramic oscillation mode ? fosc1=4mhz ? system clock: fosc1 ? internal rc oscillation stopped ? fosc0=0hz (oscillation stop) ? 1/2 frequency division ratio. 2.4 to 3.6 2200 2900 iddop(7) 2.3 to 5.5 1900 3000 iddop(8) internal rc oscillation mode ? system clock: internal rc ? internal rc oscillates ? fosc0=0hz (oscillation stop) ? fosc1=0hz (oscillation stop) ? 1/1 frequency division ratio 2.3 to3.6 1200 2000 iddop(9) 2.3 to 5.5 1700 2300 iddop(10) high-speed rc oscillation mode *ta=0 to 60 c ? fosc1=1mhz rcr1=470k ? system clock: fosc1 ? internal rc oscillation stopped ? fosc0=0hz (oscillation stop) ? 1/1 frequency division ratio. 2.3 to 3.6 1200 1700 iddop(11) 2.3 to 5.5 110 170 consumption current during normal operation (note 8-1) iddop(12) v dd low-speed rc oscillation mode *ta=0 to 60 c ? fosc0=64khz rcr0=910k ? system clock: fosc0 ? internal rc oscillation stopped ? fosc1=0hz (oscillation stop) ? 1/1 frequency division ratio. 2.3 to 3.6 70 110 a note 8-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
lc88f83b0a no.a1228-21/25 continued from preceding page. specification parameter symbol pin/ remarks condition v dd [v] min typ max unit iddhalt(1) 2.4 to 5.5 32 93 iddhalt(2) lcd display on 2.4 to 3.6 15 35 iddhalt(3) 2.3 to 5.5 22 59 iddhalt(4) halt mode crystal oscillation mode ? fosc0=32.768khz ? system clock: fosc0 ? internal rc oscillation stopped ? fosc1=0hz (oscillation stop) ? 1/1frequency division ratio. [no panel load] lcd display off 2.3 to 3.6 6 21 iddhalt(5) 2.4 to 5.5 700 1100 iddhalt(6) halt mode ceramic oscillation mode ? fosc1=4mhz ? system clock: fosc1 ? internal rc oscillation stopped ? fosc0=0hz (oscillation stop) ? 1/2 frequency division ratio. 2.4 to 3.6 300 500 iddhalt(7) 2.3 to 5.5 400 700 iddhalt(8) halt mode internal rc oscillation mode ? system clock: internal rc ? internal rc oscillates ? fosc0=0hz (oscillation stop) ? fosc1=0hz (oscillation stop) ? 1/1 frequency division ratio. 2.3 to 3.6 200 300 iddhalt(9) 2.3 to 5.5 200 400 iddhalt(10) halt mode high-speed rc oscillation mode *ta=0 to 60 c ? fosc1=1mhz rcr1=470k ? system clock: fosc1 ? internal rc oscillation stopped ? fosc0=0hz (oscillation stop) ? 1/1 frequency division ratio. 2.3 to 3.6 100 200 iddhalt(11) 2.3 to 5.5 20 50 consumption current during halt mode (note 8-1) iddhalt(12) v dd halt mode low-speed rc oscillation mode *ta=0 to 60 c ? fosc0=64khz rcr0=910k ? system clock: fosc0 ? internal rc oscillation stopped ? fosc1=0hz (oscillation stop) ? 1/1 frequency division ratio. 2.3 to 3.6 10 30 iddhold(1) 2.3 to 5.5 12 consumption current during hold mode iddhold(2) v dd hold mode ? cf1=v dd or open (external clock mode) 2.3 to 3.6 5 iddhold(3) 2.3 to 5.5 16 55 consumption current during clock hold mode iddhold(4) v dd clock hold mode ? cf1=v dd or open (external clock mode) ? fmx?tal=32.768khz crystal oscillation mode 2.3 to 3.6 3 16 a note 8-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. f-rom programming characteristics at ta = +10 c to +55 c, v ss = lcdv ss 0 = lcdv ss 1 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd the consumption current of the microcomputer is excluded. 2.7 to 5.5 5 10 ma tfw(1) erasing time: 128 bytes 2.7 to 5.5 20 30 ms programming time tfw(2) programming time: 2 bytes 2.7 to 5.5 40 60 s
lc88f83b0a no.a1228-22/25 characteristics of a sample osc1 system clock oscillation circuit given below are the characteristics of a sample osc1 syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample osc1 system clock oscillator circuit with a ceramic oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks cstcr4m00g53-r0 (15) (15) open 0 2.4 to 5.5 0.1 0.5 4.194mhz murata cstls4m00g53-b0 (15) (15) open 0 2.4 to 5.5 0.1 0.5 internal c1,c2 cstcr4m00g53-r0 (15) (15) open 0 2.4 to 5.5 0.1 0.5 4.000mhz murata cstls4m00g53-b0 (15) (15) open 0 2.4 to 5.5 0.1 0.5 internal c1,c2 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the following reference timing points: (see figure 4) ? v dd goes above the operating voltage lower limit. ? an instruction for starting the osc1 clock oscillator circuit is executed. ? oscillation starts after the microcontro ller exits the x'tal hold mode with the enosc1 bit (ocr0 register, bit 1) set to 1. characteristics of a sample osc0 system clock oscillator circuit given below are the characteristics of a sample osc0 syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample osc0 system clock oscillator circuit with a cf oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 open 390k 2.3 to 5.5 1.3 3.0 applicable cl value=12.5pf smd-type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the osc0 clock oscilla tion circuit is executed. (see figure 4) note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd cf2 cf1 c1 rd1 c2 cf rf1 c3 rd2 c4 x?tal xt2 xt1 rf2
lc88f83b0a no.a1228-23/25 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization time internal rc oscillation cf1, cf2 xt1, xt2 state hold reset signal hold reset signal absent hold reset signal valid tmscf tmsx?tal hold halt power supply resb internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd 0v operating v dd lower limit
lc88f83b0a no.a1228-24/25 figure 5 reset circuit *: remarks: dix and dox are the final communication bits. x = 0 to 32768 figure 6 serial i/o waveforms figure 7 pulse input timing signal waveform c res v dd r res resb tpil tpih note: select c res and r res values to assure that at least 50 s reset time is provided after the v dd becomes higher than the minimum operating voltage. dataout: dataout: dataout: data ram transfer period (sio0 only) data ram transfer period (sio0 only) di0 di7 dix di8 do0 do7 dox do8 di1 do1 sioclk: datain: datain: sioclk: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo tsckhbsy run: di6 do6 tsckhbsy
lc88f83b0a no.a1228-25/25 note: the oscillation frequency changes with the board patter n and used parts when osc1 and osc0 are used as the rc oscillation. it also greatly depends on the product sh ape (chip and plastic package) and the board capacitance, and it is recommended to evaluate the resistor value with an actual product. use the following characteristics as only for a reference. figure 8 characteristics of resistor v.s. frequency of osc1 figure 9 characteri stics of resistor v.s. frequency of osc0 ps this catalog provides information as of march, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. 2 0.1 200 1000 800 0 400 600 1200 frequency - resistor resistor - k frequency - mhz ilc05650 5 10 3 1.0 7 2 5 3 7 ta=25 c, typ 2 10 200 1000 800 0 400 600 1200 frequency - resistor resistor - k frequency - khz ilc05651 5 1000 3 100 7 2 5 3 7 ta=25 c, typ

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